MICROCONTROLLER SOLUTIONS

Controller Boasts LCD, USB OTG and Ethernet Interfaces

The LPC3250 microcontroller from NXP Semiconductors addresses embedded applications that require high performance and low power consumption. Based on an ARM926EJ-S CPU core, the device integrates a Vector Floating Point (VFP) co-processor, a wide range of peripherals including an LCD controller and USB On-The-Go (OTG), and SDRAM and NAND Flash interfaces.



The device runs at clock speeds of up to 208MHz. Its ARM926EJ-S core uses a Harvard architecture with a five-stage pipeline, and a set of DSP instruction extensions including single cycle MAC operations and native Jazelle Java byte-code execution in hardware. The NXP implementation includes 32KByte instruction and data caches, and is equipped with an integral memory management unit to support the needs of applications based on embedded operating systems.

The VFP coprocessor increases the speed of typical calculations by a factor of four to five in scalar mode, and much more in optimised vector mode. Like all members of the NXP LPC32x0 series, the LPC3250 uses advanced 90nm process technology to optimise intrinsic power and includes software-controlled features that provide best-in-class power management.

The device features 256KByte of on-chip static RAM and an external memory controller that supports DDR and SDR SDRAM, SRAM, Flash, and static devices. The external-memory controller can boot from NAND Flash, SPI memory, UART, or SRAM.

The on-chip 24-bit LCD controller with dedicated DMA supports both STN and TFT panels with programmable display resolution up to 1024 pixels x 768 pixels and up to 16 million colours. A 10-bit A/D Converter with touch-screen interface increases flexibility and integration.



In addition to its full-speed USB 2.0 interface, the LPC3250 includes an Ethernet MAC, seven UARTs, two I²C interfaces, two SPI/SSP ports, two I²S interfaces, two multi-channel PWMs, four general-purpose timers with capture inputs and a Secure Digital (SD) interface.

An on-chip Phase-Locked Loop (PLL) allows the CPU to operate up to its maximum rate without a high-frequency crystal. A second PLL enables operation from the 32kHz real-time clock instead of an external crystal. While the core logic operates at 1.2V (down to 0.9V in ultra-low-power mode), the I/O ports support 1.8V, 2.8V and 3.0V operation. Operating temperature range is -40°C to +85°C and the device is supplied in a compact 15mm x 15mm x 0.8mm 296-terminal Thin Fine-pitch Ball Grid Array (TFBGA) package.

Features

• 208MHz ARM9-based microcontroller
• Vector floating point co-processor
• 32KByte instruction and data caches
• Memory management unit
• Low operating power
  • Core voltage down to 0.9V
• Software-controlled power management
• 256KByte SRAM
• Memory controller supports DDR and SDR SDRAM, SRAM, NAND Flash, static devices
• Bootable from NAND Flash, SPI, UART, SRAM
• 24-bit LCD controller with dedicated DMA
  • Supports both STN and TFT panels
  • Touch-screen functionality
• USB 2.0/OTG
• Ethernet MAC
• Multiple UARTs, I²C, SPI/SSP, I²S, SD interfaces
• Two multi-channel PWMs and four timers with capture inputs
• Two phase-locked loops
• I/Os support 1.8V, 2.8V and 3.0V operation
• 15mm x 15mm x 0.8mm 296-terminal TFBGA

Applications

• Consumer products
• Medical
• Industrial
• Automotive
• Network control
• Communication

For further information, including a copy of the LPC32x0 Family Datasheet, please click here